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Philips Semiconductors
Product specification
PowerMOS transistor Logic level TOPFET
DESCRIPTION
Monolithic temperature and overload protected logic level power MOSFET in a 5 pin plastic envelope, intended as a general purpose switch for automotive systems and other applications.
BUK104-50L/S BUK104-50LP/SP
QUICK REFERENCE DATA
SYMBOL VDS ID Ptot Tj RDS(ON) PARAMETER Continuous drain source voltage Continuous drain current Total power dissipation Continuous junction temperature Drain-source on-state resistance VIS = 5 V VIS = 7 V PARAMETER Protection supply voltage BUK104-50L BUK104-50S MAX. 50 15 40 150 125 100 NOM. 5 10 UNIT V A W C m m UNIT V V
APPLICATIONS
General controller for driving lamps motors solenoids heaters
SYMBOL VPSN
FEATURES
Vertical power DMOS output stage Low on-state resistance Logic and protection supply from separate pin Low operating supply current Overload protection against over temperature Overload protection against short circuit load Latched overload protection reset by protection supply Protection circuit condition indicated by flag pin 5 V logic compatible input level Separate input pin for higher frequency drive ESD protection on input, flag and protection supply pins Over voltage clamping for turn off of inductive loads Both linear and switching operation are possible
FUNCTIONAL BLOCK DIAGRAM
PROTECTION SUPPLY DRAIN
FLAG
O/V CLAMP POWER MOSFET
INPUT
LOGIC AND PROTECTION
SOURCE
Fig.1. Elements of the TOPFET.
PINNING - SOT263
PIN 1 2 3 4 5 tab input flag drain protection supply source drain DESCRIPTION
PIN CONFIGURATION
tab
SYMBOL
D TOPFET P F I
P
1 2345
leadform 263-01
Fig. 2. Type numbers ending with suffix P refer to leadform 263-01.
S
Fig. 3.
January 1993
1
Rev 1.200
Philips Semiconductors
Product specification
PowerMOS transistor Logic level TOPFET
LIMITING VALUES
Limiting values in accordance with the Absolute Maximum Rating System (IEC 134) SYMBOL VDSS VIS VFS VPS ID ID IDRM Ptot Tstg Tj Tsold PARAMETER Voltages Continuous off-state drain source voltage1 Continuous input voltage Continuous flag voltage Continuous supply voltage Currents Continuous drain current Continuous drain current Repetitive peak on-state drain current Thermal Total power dissipation Storage temperature Junction temperature2 Lead temperature Tmb 25 C Tmb 100 C Tmb 25 C Tmb = 25 C continuous during soldering CONDITIONS VIS = 0 V VIS =
BUK104-50L/S BUK104-50LP/SP
MIN. 0 0 0 -55 -
MAX. 50 11 11 11 7 5 15 13 9.5 8.5 60 54 40 150 150 250
UNIT V V V V V A A A W C C C
OVERLOAD PROTECTION LIMITING VALUES
With the protection supply connected, TOPFET can protect itself from two types of overload over temperature and short circuit load. SYMBOL VPSP PARAMETER Protection supply voltage
3
An n-MOS transistor turns on between the input and source to quickly discharge the power MOSFET gate capacitance. CONDITIONS
For internal overload protection to remain latched while the control circuit is high, external series input resistance must be provided. Refer to INPUT CHARACTERISTICS. MIN. VIS = 7 4.4 5.4 5 4 5 MAX. 50 50 25 45 0.8 UNIT V V V V V V V kW
for valid protection BUK104-50L BUK104-50S
VDDP(T)
Over temperature protection VPS = VPSN Protected drain source supply voltage VIS = 10 V; RI 2 k VIS = 5 V; RI 1 k Short circuit load protection VPS = VPSN; L 10 H Protected drain source supply voltage4 VIS = 10 V; RI 2 k VIS = 5 V; RI 1 k Instantaneous overload dissipation
VDDP(P) PDSM
ESD LIMITING VALUE
SYMBOL VC PARAMETER Electrostatic discharge capacitor voltage CONDITIONS Human body model; C = 250 pF; R = 1.5 k MIN. MAX. 2 UNIT kV
1 Prior to the onset of overvoltage clamping. For voltages above this value, safe operation is limited by the overvoltage clamping energy. 2 A higher Tj is allowed as an overload condition but at the threshold Tj(TO) the over temperature trip operates to protect the switch. 3 The minimum supply voltage required for correct operation of the overload protection circuits. 4 The device is able to self-protect against a short circuit load providing the drain-source supply voltage does not exceed VDDP(P) maximum. For further information, refer to OVERLOAD PROTECTION CHARACTERISTICS.
January 1993
2
Rev 1.200
Philips Semiconductors
Product specification
PowerMOS transistor Logic level TOPFET
OVERVOLTAGE CLAMPING LIMITING VALUES
BUK104-50L/S BUK104-50LP/SP
At a drain source voltage above 50 V the power MOSFET is actively turned on to clamp overvoltage transients. SYMBOL IDRRM EDSM EDRM PARAMETER CONDITIONS
1
MIN. -
MAX. 15 200 20
UNIT A mJ mJ
Repetitive peak clamping drain current RIS 100 Non-repetitive inductive turn-off IDM = 15 A; RIS 100 energy2 Repetitive inductive turn-off energy RIS 100 ; Tmb 95 C; IDM = 4 A; VDD 20 V; f = 250 Hz Repetitive peak drain to input current3 RIS = 0 ; tp 1 ms
IDIRM
-
50
mA
REVERSE DIODE LIMITING VALUE
SYMBOL IS PARAMETER Continuous forward current CONDITIONS Tmb = 25 C; VIS = VPS = VFS = 0 V MIN. MAX. 15 UNIT A
THERMAL CHARACTERISTICS
SYMBOL Rth j-mb Rth j-a PARAMETER Thermal resistance Junction to mounting base Junction to ambient in free air 2.5 60 3.1 K/W K/W CONDITIONS MIN. TYP. MAX. UNIT
STATIC CHARACTERISTICS
Tmb = 25 C unless otherwise specified SYMBOL V(CL)DSR V(CL)DSR IDSS IDSR IDSR RDS(ON) PARAMETER Drain-source clamping voltage Drain-source clamping voltage CONDITIONS RIS = 100 ; ID = 10 mA MIN. 50 50 TYP. 0.5 1 10 75 95 MAX. 65 70 10 20 100 100 125 UNIT V V A A A m m
RIS = 100 ; IDM = 1 A; tp 300 s; 0.01 Zero input voltage drain current VDS = 12 V; VIS = 0 V Drain source leakage current VDS = 50 V; RIS = 100 ; Drain source leakage current VDS = 40 V; RIS = 100 ; Tj = 125 C Drain-source on-state resistance IDM = 7.5 A; tp 300 s; 0.01 VIS = 7 V VIS = 5 V
1 The input pin must be connected to the source pin by a specified external resistance to allow the power MOSFET gate source voltage to become sufficiently positive for active clamping. Refer to INPUT CHARACTERISTICS. 2 While the protection supply voltage is connected, during overvoltage clamping it is possible that the overload protection may operate at energies close to the limiting value. Refer to OVERLOAD PROTECTION CHARACTERISTICS. 3 Shorting the input to source with low resistance inhibits the internal overvoltage protection by preventing the power MOSFET gate source voltage becoming positive.
January 1993
3
Rev 1.200
Philips Semiconductors
Product specification
PowerMOS transistor Logic level TOPFET
OVERLOAD PROTECTION CHARACTERISTICS
With adequate protection supply voltage TOPFET detects when one of the overload thresholds is exceeded. SYMBOL PARAMETER Short circuit load protection EDS(TO) td sc Tj(TO) Overload threshold energy Response time
1
BUK104-50L/S BUK104-50LP/SP
Provided there is adequate input series resistance it switches off and remains latched off until reset by the protection supply pin. CONDITIONS
2 PSN
Refer also to OVERLOAD PROTECTION LIMITING VALUES and INPUT CHARACTERISTICS. MIN. TYP. MAX. UNIT
VPS = V ; Tmb = 25 C; L 10 H; RI 2 k VDD = 13 V; VIS = 10 V VDD = 13 V; VIS = 10 V
150
150 375 -
-
mJ s C
Over temperature protection VPS = VPSN; RI 2 k Threshold junction temperature from ID 0.65 A3
TRANSFER CHARACTERISTICS
Tmb = 25 C SYMBOL gfs ID PARAMETER Forward transconductance Drain current4 CONDITIONS VDS = 10 V; IDM = 7.5 A tp 300 s; 0.01 VDS = 13 V; VIS = 5 V VIS = 10 V MIN. 5 TYP. 9 25 40 MAX. UNIT S A A
PROTECTION SUPPLY CHARACTERISTICS
Tmb = 25 C unless otherwise specified SYMBOL IPS, IPSL PARAMETER Protection supply Protection supply current CONDITIONS normal operation or protection latched BUK104-50L BUK104-50S Tj = 150 C V(CL)PS Protection clamp voltage IP = 1.35 mA MIN. TYP. MAX. UNIT
VPSR
Protection reset voltage5
VPS = 5 V VPS = 10 V
1.5 1.0 11
0.2 0.4 2.5 13
0.35 1.0 3.5 -
mA mA V V V
REVERSE DIODE CHARACTERISTICS
Tmb = 25 C SYMBOL VSDS trr PARAMETER Forward voltage Reverse recovery time CONDITIONS IS = 15 A; VIS = VPS = VFS = 0 V; tp = 300 s not applicable6 MIN. TYP. 1.0 MAX. 1.5 UNIT V -
1 The short circuit load protection is able to save the device providing the instantaneous on-state dissipation is less than the limiting value for PDSM, which is always the case when VDS is less than VDSP maximum. 2 At the appropriate nominal protection supply voltage for each type. Refer to QUICK REFERENCE DATA. 3 The over temperature protection feature requires a minimum on-state drain source voltage for correct operation. The specified minimum ID ensures this condition. 4 During overload condition. Refer also to OVERLOAD PROTECTION LIMITING VALUES and CHARACTERISTICS. 5 The supply voltage below which the overload protection circuits will be reset. 6 The reverse diode of this type is not intended for applications requiring fast reverse recovery.
January 1993
4
Rev 1.200
Philips Semiconductors
Product specification
PowerMOS transistor Logic level TOPFET
INPUT CHARACTERISTICS
Tmb = 25 C unless otherwise specified SYMBOL VIS(TO) IIS V(CL)IS RISL PARAMETER Normal operation Input threshold voltage Input current Input clamp voltage Overload protection latched Input resistance1 VPS = 5 V VPS = 10 V Application information External input resistances for internal overvoltage clamping2 internal overload protection
3
BUK104-50L/S BUK104-50LP/SP
CONDITIONS VDS = 5 V; ID = 1 mA Tmb = 150 C VIS = 10 V II = 1 mA II = 5 mA; Tmb = 150 C II = 5 mA; Tmb = 150 C
MIN. 1.0 0.5 11 -
TYP. 1.5 10 13 55 95 35 60
MAX. 2.0 100 -
UNIT V V nA V k k
RIS RI
(see figure 29) RI = ; RIS = ;
VDS > 30 V VII = 5 V VII = 10 V
100 1 2
-
-
SWITCHING CHARACTERISTICS
Tmb = 25 C; RI = 50 ; RIS = 50 (see figure 29); resistive load RL = 10 . For waveforms see figure 28. SYMBOL td on tr td off tf PARAMETER Turn-on delay time Rise time Turn-off delay time Fall time VDD = 15 V; VIS: 10 V 0 V CONDITIONS VDD = 15 V; VIS: 0 V 10 V MIN. TYP. 8 13 100 45 MAX. UNIT ns ns ns ns
CAPACITANCES
Tmb = 25 C; f = 1 MHz SYMBOL Ciss Coss Crss Cpso Cfso PARAMETER Input capacitance Output capacitance Reverse transfer capacitance Protection supply pin capacitance Flag pin capacitance CONDITIONS VDS = 25 V; VIS = 0 V VDS = 25 V; VIS = 0 V VDS = 25 V; VIS = 0 V VPS = 10 V VFS = 10 V; VPS = 0 V MIN. TYP. 415 275 55 30 20 MAX. 600 400 80 UNIT pF pF pF pF pF
1 The resistance of the internal transistor which discharges the power MOSFET gate capacitance when overload protection operates. The external drive circuit should be such that the input voltage does not exceed VIS(TO) minimum when the overload protection has operated. Refer also to figure for latched input characteristics. 2 Applications using a lower value for RIS would require external overvoltage protection. 3 For applications requiring a lower value for RI, an external overload protection strategy is possible using the flag pin to `tell' the control circuit to switch off the input.
January 1993
5
Rev 1.200
Philips Semiconductors
Product specification
PowerMOS transistor Logic level TOPFET
FLAG DESCRIPTION
The flag pin provides a means to detect the presence of the protection supply and indicate the state of the overload detectors. The flag is the open drain of an n-MOS transistor and requires an external pull-up resistor1. It is suitable for both 5 V and 10 V logic. Flag may be used to implement an external protection strategy2 for applications which require low input drive impedance.
BUK104-50L/S BUK104-50LP/SP
TRUTH TABLE
CONDITION NORMAL OVER TEMP. SHORT CIRCUIT SUPPLY FAULT DESCRIPTION Normal operation and adequate protection supply voltage Over temperature detected Overload condition detected Inadequate protection supply voltage FLAG LOGIC LOW LOGIC HIGH LOGIC HIGH LOGIC HIGH
FLAG CHARACTERISTICS
Tmb = 25 C unless otherwise stated SYMBOL VFS IFSS IFS VPSF PARAMETER Flag `low' Flag voltage Flag saturation current Flag `high' Flag leakage current Protection supply threshold voltage Flag clamping voltage Application information RF Suitable external pull-up resistance VFF =5 V VFF =10 V 1 2 10 20 50 100 k k CONDITIONS normal operation IF = 1.6 mA VFS = 10 V overload or fault VFS = 10 V VFF = 5 V; RF = 3 k; MIN. BUK104-50L BUK104-50S 2.5 3.3 11 TYP. 0.15 15 3.3 4.2 13 MAX. 0.4 10 4 5 UNIT V mA A V V V
V(CL)FS
IF = 1 mA; VPS = 0 V
ENVELOPE CHARACTERISTICS
SYMBOL Ld Ld Ls PARAMETER Internal drain inductance Internal drain inductance Internal source inductance CONDITIONS Measured from contact screw on tab to centre of die Measured from drain lead 6 mm from package to centre of die Measured from source lead 6 mm from package to source bond pad MIN. TYP. 3.5 4.5 7.5 MAX. UNIT nH nH nH
1 Even if the flag pin is not used, it is recommended that it is connected to the protection supply via a pull-up resistor. It should not be left floating. 2 Low pass filtering of the flag signal may be advisable to prevent false tripping.
January 1993
6
Rev 1.200
Philips Semiconductors
Product specification
PowerMOS transistor Logic level TOPFET
BUK104-50L/S BUK104-50LP/SP
120 110 100 90 80 70 60 50 40 30 20 10 0
PD%
Normalised Power Derating
10
Zth / (K/W)
BUK104-50L/S
D= 0.5 1 0.2 0.1 0.05 0.1 0.02
P D tp D= tp T t
0
0
20
40
60
80 100 Tmb / C
120
140
0.01 1E-07
T
1E-05
1E-03 t/s
1E-01
1E+01
Fig.4. Normalised limiting power dissipation. PD% = 100PD/PD(25 C) = f(Tmb)
ID% Normalised Current Derating
50
Fig.7. Transient thermal impedance. Zth j-mb = f(t); parameter D = tp/T
ID / A BUK104-50L/S VIS / V = 40 10 9 30 8 7 6 20 5 4 3 2 0 0 4 8 12 16 VDS / V 20 24 28 32
120 110 100 90 80 70 60 50 40 30 20 10 0
10
0
20
40
60
80 Tmb / C
100
120
140
Fig.5. Normalised continuous drain current. ID% = 100ID/ID(25 C) = f(Tmb); conditions: VIS = 5 V
ID & IDM / A
=V D D S/I
Fig.8. Typical output characteristics, Tj = 25 C. ID = f(VDS); parameter VIS; tp = 250 s & tp < td sc
ID / A VIS / V = 10 BUK104-50L/S 7 6 5 15
100
BUK104-50L/S tp = 10 us 100 us
20
RD
O S(
N)
10
4
1 ms DC 1 10 ms 100 ms
10
5 3
Overload protection characteristics not shown 0.1 1 10 VDS / V 100
0 0 1 VDS / V 2
Fig.6. Safe operating area. Tmb = 25 C ID & IDM = f(VDS); IDM single pulse; parameter tp
Fig.9. Typical on-state characteristics, Tj = 25 C. ID = f(VDS); parameter VIS; tp = 250 s
January 1993
7
Rev 1.200
Philips Semiconductors
Product specification
PowerMOS transistor Logic level TOPFET
BUK104-50L/S BUK104-50LP/SP
150
RDS(ON) / mOhm VIS / V = 4
BUK104-50L/S
a
Normalised RDS(ON) = f(Tj)
5 100 6 7 10 50
1.5
1.0
0.5
0 0 2 4 6 8 10 ID / A 12 14 16 18 20
0
-60 -40 -20
0
20
40 60 Tj / C
80
100 120 140
Fig.10. Typical on-state resistance, Tj = 25 C. RDS(ON) = f(ID); parameter VIS; tp = 250 s
ID / A BUK104-50L/S
Fig.13. Normalised drain-source on-state resistance. a = RDS(ON)/RDS(ON)25 C = f(Tj); ID = 7.5 A; VIS 5 V
Tj(TO) / C BUK104-50L/S
50
230 220
40
210 200 190
BUK104-50S
30
20
180 170
10
160
BUK104-50L
0 0 2 4 6 VIS / V 8 10 12
150 0 2 4 6 VPS / V 8 10
Fig.11. Typical transfer characteristics, Tj = 25 C. ID = f(VIS) ; conditions: VDS = 10 V; tp = 250 s
gfs / S BUK104-50L/S
Fig.14. Typical over temperature protection threshold Tj(TO) = f(VPS); conditions: VDS > 0.1 V
PDSM% 120 100 80 60 40 20 0
10 9 8 7 6 5 4 3 2 1 0
0
10
20 ID / A
30
40
50
-60
-40
-20
0
20
40 60 Tmb / C
80
100
120
140
Fig.12. Typical transconductance, Tj = 25 C. gfs = f(ID); conditions: VDS = 10 V; tp = 250 s
Fig.15. Normalised limiting overload dissipation. PDSM% =100PDSM/PDSM(25 C) = f(Tmb)
January 1993
8
Rev 1.200
Philips Semiconductors
Product specification
PowerMOS transistor Logic level TOPFET
BUK104-50L/S BUK104-50LP/SP
50
VDDP(P) / V
BUK104-50L/S
0.5
Energy & Time
BUK104-50L/S
40
0.4
max
30
0.3
Time / ms
20
0.2
10
0.1
Energy / J Tj(TO)
0 0 2 4 6 VIS / V 8 10
0 -60 -20 20 60 100 Tmb / C 140 180 220
Fig.16. Maximum drain source supply voltage for SC load protection. VDDP(P) = f(VIS); Tmb 150 C
VPSP / V 10 8 6 4
BUK104-50L BUK104-50S
Fig.19. Typical overload protection characteristics. Conditions: VDD = 13 V; VPS = VPSN, VIS = 7 V; SC load
ESC(TO) / J BUK104-50L/S
BUK104-50L/S
0.4
0.3
BUK104-50L VIS / V = 5
min
0.2
10 5 10
0.1
BUK104-50S
2 0 0 2 4 6 VIS / V 8 10
0 0 2 4 6 VPS / V 8 10
Fig.17. Minimum protection supply voltage for SC load protection. VPSP = f(VIS); Tmb 25 C
TIME / ms BUK104-50L/S
Fig.20. Typical overload protection energy, Tj = 25 C ESC(TO) = f(VPS); conditions: VDS = 13 V, parameter VIS
ID / A BUK104-50L/S
10
20
15
1 PDSM
10
typ.
5
0.1 0.1 1 POWER / kW 10
0 50 60 VDS / V 70
Fig.18. Typical overload protection characteristics. td sc = f(PDS); conditions: VPS VPSP; VIS 5 V
Fig.21. Typical clamping characteristics, 25 C. ID = f(VDS); conditions: RIS = 100 ; tp 50 s
January 1993
9
Rev 1.200
Philips Semiconductors
Product specification
PowerMOS transistor Logic level TOPFET
BUK104-50L/S BUK104-50LP/SP
VIS(TO) / V
20
max.
IS / A
BUK104-50L/S
2
15
typ.
1
min.
10
5
0 -60 -40 -20 0 20 40 60 Tj / C 80 100 120 140
0 0 0.5 VSD / V 1 1.5
Fig.22. Input threshold voltage. VIS(TO) = f(Tj); conditions: ID = 1 mA; VDS = 5 V
IPS / mA BUK104-50L/S
Fig.25. Typical reverse diode current, Tj = 25 C. IS = f(VSDS); conditions: VIS = 0 V; tp = 250 s
EDSM%
1.0
120 110 100 90 80 70
0.5
60 50 40 30 20 10
0 0 2 4 6 VPS / V 8 10 12 14
0 0 20 40 60 80 Tmb / C 100 120 140
Fig.23. Typical DC protection supply characteristics. IPS = f(VPS); normal or overload operation; Tj = 25 C
IISL / mA 150 VPS / V = 11 10 9 100 8 7 6 50 5 4 BUK104-50L/S
Fig.26. Normalised limiting clamping energy. EDSM% = f(Tmb); conditions: ID = 15 A
V(CL)DSR VDS VDD 0 ID 0 VIS 0 RI = RIS
RF
P F I
P
+
L VDS
D TOPFET
VDD
+ VPS
-ID/100 D.U.T. R 01 shunt
S
0 0 2 4 6 VIS / V 8 10
Fig.24. Typical latched input characteristics, 25 C. IISL = f(VIS); after overload protection latched
Fig.27. Clamping energy test circuit, RIS = 100 . 2 EDSM = 0.5 LID V(CL)DSR /(V(CL)DSR - VDD )
January 1993
10
Rev 1.200
Philips Semiconductors
Product specification
PowerMOS transistor Logic level TOPFET
BUK104-50L/S BUK104-50LP/SP
VIS / V & VDS / V 15 VDS VIS 10
BUK104-50L/S
1 mA
Idsr
100 uA
10 uA
typ.
5
1 uA
0
100 nA
0 0.5 time / us 1
0
20
40
60
80 Tj / C
100
120
140
Fig.28. Typical resistive load switching waveforms RI = RIS = 50 ; RL = 10 ; VDD = 15 V; Tj = 25 C
Fig.31. Typical off-state leakage current. IDSR = f(Tj); Conditions: VDS = 40 V; RIS = 100 .
Ips normalised to 25 C
VII
1.5
RI VIS
D TOPFET P F I
P
1
S
RIS
0.5 -60 -20 20 60 Tj / C 100 140 180
Fig.29. External input resistances RI and RIS, generator voltage VII and input voltage VIS.
Capacitance / pF BUK104-50L/S
Fig.32. Normalised protection supply current. IPS/IPS25 C = f(Tj); VPS = VPSN
10000
1000 Ciss
Coss 100 Crss
10 0 10 20 VDS / V 30 40 50
Fig.30. Typical capacitances, Ciss, Coss, Crss. C = f(VDS); conditions: VIS = 0 V; f = 1 MHz
January 1993
11
Rev 1.200
Philips Semiconductors
Product specification
PowerMOS transistor Logic level TOPFET
MECHANICAL DATA
Dimensions in mm Net Mass: 2 g
BUK104-50L/S BUK104-50LP/SP
4.5 max
10.3 max
1.3
3.6 2.8
mounting base
5.9 min
15.8 max
2.4 max
(2)
3.5 max not tinned
0.5 0.6 min (4 x) 1.7
(4 x)
12 3 45
(1) M
(1)
13.5 min
0.4
0.9 max
(5 x) NOTES (1) (2)
0.6 2.4
positional accuracy of the terminals is controlled in this zone only. terminal dimensions in this zone are uncontrolled.
Fig.33. SOT263 ( 5-pin TO220 ); pin 3 connected to mounting base.
Note 1. Refer to mounting instructions for TO220 envelopes. 2. Epoxy meets UL94 V0 at 1/8".
January 1993
12
Rev 1.200
Philips Semiconductors
Product specification
PowerMOS transistor Logic level TOPFET
MECHANICAL DATA
Dimensions in mm Net Mass: 2 g
BUK104-50L/S BUK104-50LP/SP
4.5 max
10.3 max
1.3
3.6 2.8
mounting base
5.9 min
3.5 max not tinned
R
0.
(2)
5
m
2.4 max
15.8 max
in
5.6
0.5
12 3 45
(1)
9.75
0. 5 m in
5
R
0.6 min (4 x) 0.9 max
(5 x) NOTES (1) (2)
1.7
(4 x)
0.6
4.5
2.4
0.4
(1) M
8.2
positional accuracy of the terminals is controlled in this zone only. terminal dimensions in this zone are uncontrolled.
Fig.34. SOT263 leadform 263-01; pin 3 connected to mounting base.
Note 1. Refer to mounting instructions for TO220 envelopes. 2. Epoxy meets UL94 V0 at 1/8".
January 1993
13
Rev 1.200
Philips Semiconductors
Product specification
PowerMOS transistor Logic level TOPFET
DEFINITIONS
Data sheet status Objective specification Product specification Limiting values
BUK104-50L/S BUK104-50LP/SP
This data sheet contains target or goal specifications for product development. This data sheet contains final product specifications.
Preliminary specification This data sheet contains preliminary data; supplementary data may be published later.
Limiting values are given in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of this specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information Where application information is given, it is advisory and does not form part of the specification. (c) Philips Electronics N.V. 1996 All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. The information presented in this document does not form part of any quotation or contract, it is believed to be accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license under patent or other industrial or intellectual property rights.
LIFE SUPPORT APPLICATIONS
These products are not designed for use in life support appliances, devices or systems where malfunction of these products can be reasonably expected to result in personal injury. Philips customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such improper use or sale.
January 1993
14
Rev 1.200

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